ARM st ate general registers and program counter r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r1 1 r12 r13 r14 r15 (PC) System and User CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und ARM st ate program st atus registers = banked register r0 r1 r2 r3 r4 r5 r6 r7 r8 _fiq r9 _fiq r10 _fiq r1 1 _fiq r12 _fiq r13 _fiq r14_fiq r15 (PC) FIQ r0 r1 r2 r3 r4 r5 r6 r7 r13 _svc r14_svc r15 (PC) Supervisor r8 r9 r10 r1 1 r12 r0 r1 r2 r3 r4 r5 r6 r7 r13 _abt r14_abt r15 (PC) Abort r8 r9 r10 r1 1 r12 r0 r1 r2 r3 r4 r5 r6 r7 r13 _irq r14_irq r15 (PC) IRQ r8 r9 r10 r1 1 r12 r0 r1 r2 r3 r4 r5 r6 r7 r13 _und r14_und r15 (PC) Undefined r8 r9 r10 r1 1 r12