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ARM/ELF: Better codegen for global variable addresses.
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In PIC mode we were previously computing global variable addresses (or GOT
entry addresses) by adding the PC, the PC-relative GOT displacement and
the GOT-relative symbol/GOT entry displacement. Because the latter two
displacements are fixed, we ended up performing one more addition than
necessary.

This change causes us to compute addresses using a single PC-relative
displacement, resulting in a shorter code sequence. This reduces code size
by about 4% in a recent build of Chromium for Android.

As a result of this change we no longer need to compute the GOT base address
in the ARM backend, which allows us to remove the Global Base Reg pass and
SDAG lowering for the GOT.

We also now no longer use the GOT when addressing a symbol which is known
to be defined in the same linkage unit. Specifically, the symbol must have
either hidden visibility or a strong definition in the current module in
order to not use the the GOT.

This is a change from the previous behaviour where we would use the GOT to
address externally visible symbols defined in the same module. I think the
only cases where this could matter are cases involving symbol interposition,
but we don't really support that well anyway.

Differential Revision: http://reviews.llvm.org/D13650

llvm-svn: 251322
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@pcc
pcc committed Oct 26, 2015
1 parent 871d324 commit 97aae40
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Showing 19 changed files with 106 additions and 235 deletions.
1 change: 1 addition & 0 deletions llvm/include/llvm/MC/MCExpr.h
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Expand Up @@ -188,6 +188,7 @@ class MCSymbolRefExpr : public MCExpr {
VK_WEAKREF, // The link between the symbols in .weakref foo, bar

VK_ARM_NONE,
VK_ARM_GOT_PREL,
VK_ARM_TARGET1,
VK_ARM_TARGET2,
VK_ARM_PREL31,
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3 changes: 2 additions & 1 deletion llvm/lib/MC/MCExpr.cpp
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Expand Up @@ -202,6 +202,7 @@ StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) {
case VK_SIZE: return "SIZE";
case VK_WEAKREF: return "WEAKREF";
case VK_ARM_NONE: return "none";
case VK_ARM_GOT_PREL: return "GOT_PREL";
case VK_ARM_TARGET1: return "target1";
case VK_ARM_TARGET2: return "target2";
case VK_ARM_PREL31: return "prel31";
Expand Down Expand Up @@ -311,7 +312,6 @@ MCSymbolRefExpr::getVariantKindForName(StringRef Name) {
.Case("got", VK_GOT)
.Case("gotoff", VK_GOTOFF)
.Case("gotpcrel", VK_GOTPCREL)
.Case("got_prel", VK_GOTPCREL)
.Case("gottpoff", VK_GOTTPOFF)
.Case("indntpoff", VK_INDNTPOFF)
.Case("ntpoff", VK_NTPOFF)
Expand Down Expand Up @@ -383,6 +383,7 @@ MCSymbolRefExpr::getVariantKindForName(StringRef Name) {
.Case("got@tlsld@h", VK_PPC_GOT_TLSLD_HI)
.Case("got@tlsld@ha", VK_PPC_GOT_TLSLD_HA)
.Case("none", VK_ARM_NONE)
.Case("got_prel", VK_ARM_GOT_PREL)
.Case("target1", VK_ARM_TARGET1)
.Case("target2", VK_ARM_TARGET2)
.Case("prel31", VK_ARM_PREL31)
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1 change: 0 additions & 1 deletion llvm/lib/Target/ARM/ARM.h
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Expand Up @@ -35,7 +35,6 @@ FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
FunctionPass *createA15SDOptimizerPass();
FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
FunctionPass *createARMExpandPseudoPass();
FunctionPass *createARMGlobalBaseRegPass();
FunctionPass *createARMConstantIslandPass();
FunctionPass *createMLxExpansionPass();
FunctionPass *createThumb2ITBlockPass();
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3 changes: 1 addition & 2 deletions llvm/lib/Target/ARM/ARMAsmPrinter.cpp
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Expand Up @@ -819,8 +819,7 @@ getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
case ARMCP::GOT_PREL: return MCSymbolRefExpr::VK_ARM_GOT_PREL;
}
llvm_unreachable("Invalid ARMCPModifier!");
}
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6 changes: 3 additions & 3 deletions llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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Expand Up @@ -1379,9 +1379,9 @@ static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
// instructions, so that's probably OK, but is PIC always correct when
// we get here?
if (ACPV->isGlobalValue())
NewCPV = ARMConstantPoolConstant::
Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
ARMCP::CPValue, 4);
NewCPV = ARMConstantPoolConstant::Create(
cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, ARMCP::CPValue,
4, ACPV->getModifier(), ACPV->mustAddCurrentAddress());
else if (ACPV->isExtSymbol())
NewCPV = ARMConstantPoolSymbol::
Create(MF.getFunction()->getContext(),
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3 changes: 1 addition & 2 deletions llvm/lib/Target/ARM/ARMConstantPoolValue.cpp
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Expand Up @@ -52,8 +52,7 @@ const char *ARMConstantPoolValue::getModifierText() const {
// strings if that's legal.
case ARMCP::no_modifier: return "none";
case ARMCP::TLSGD: return "tlsgd";
case ARMCP::GOT: return "GOT";
case ARMCP::GOTOFF: return "GOTOFF";
case ARMCP::GOT_PREL: return "GOT_PREL";
case ARMCP::GOTTPOFF: return "gottpoff";
case ARMCP::TPOFF: return "tpoff";
}
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3 changes: 1 addition & 2 deletions llvm/lib/Target/ARM/ARMConstantPoolValue.h
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Expand Up @@ -39,8 +39,7 @@ namespace ARMCP {
enum ARMCPModifier {
no_modifier,
TLSGD,
GOT,
GOTOFF,
GOT_PREL,
GOTTPOFF,
TPOFF
};
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81 changes: 42 additions & 39 deletions llvm/lib/Target/ARM/ARMFastISel.cpp
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Expand Up @@ -2939,48 +2939,51 @@ bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,

unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
unsigned Align, MVT VT) {
bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
ARMConstantPoolConstant *CPV =
ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
bool UseGOT_PREL =
!(GV->hasHiddenVisibility() || GV->isStrongDefinitionForLinker());

LLVMContext *Context = &MF->getFunction()->getContext();
unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(
GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj,
UseGOT_PREL ? ARMCP::GOT_PREL : ARMCP::no_modifier,
/*AddCurrentAddress=*/UseGOT_PREL);

unsigned ConstAlign =
MF->getDataLayout().getPrefTypeAlignment(Type::getInt32PtrTy(*Context));
unsigned Idx = MF->getConstantPool()->getConstantPoolIndex(CPV, ConstAlign);

unsigned TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
unsigned Opc = isThumb2 ? ARM::t2LDRpci : ARM::LDRcp;
MachineInstrBuilder MIB =
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), TempReg)
.addConstantPoolIndex(Idx);
if (Opc == ARM::LDRcp)
MIB.addImm(0);
AddDefaultPred(MIB);

unsigned Opc;
unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
// Load value.
if (isThumb2) {
DestReg1 = constrainOperandRegClass(TII.get(ARM::t2LDRpci), DestReg1, 0);
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(ARM::t2LDRpci), DestReg1)
.addConstantPoolIndex(Idx));
Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
} else {
// The extra immediate is for addrmode2.
DestReg1 = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg1, 0);
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
DbgLoc, TII.get(ARM::LDRcp), DestReg1)
.addConstantPoolIndex(Idx).addImm(0));
Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
}
// Fix the address by adding pc.
unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
Opc = Subtarget->isThumb() ? ARM::tPICADD : UseGOT_PREL ? ARM::PICLDR
: ARM::PICADD;
DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0);
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
.addReg(TempReg)
.addImm(ARMPCLabelIndex);
if (!Subtarget->isThumb())
AddDefaultPred(MIB);

unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
if (GlobalBaseReg == 0) {
GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
AFI->setGlobalBaseReg(GlobalBaseReg);
if (UseGOT_PREL && Subtarget->isThumb()) {
unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(ARM::t2LDRi12), NewDestReg)
.addReg(DestReg)
.addImm(0);
DestReg = NewDestReg;
AddOptionalDefs(MIB);
}

unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
DestReg2 = constrainOperandRegClass(TII.get(Opc), DestReg2, 0);
DestReg1 = constrainOperandRegClass(TII.get(Opc), DestReg1, 1);
GlobalBaseReg = constrainOperandRegClass(TII.get(Opc), GlobalBaseReg, 2);
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
DbgLoc, TII.get(Opc), DestReg2)
.addReg(DestReg1)
.addReg(GlobalBaseReg);
if (!UseGOTOFF)
MIB.addImm(0);
AddOptionalDefs(MIB);

return DestReg2;
return DestReg;
}

bool ARMFastISel::fastLowerArguments() {
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48 changes: 16 additions & 32 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Expand Up @@ -788,7 +788,6 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,

setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
setOperationAction(ISD::BlockAddress, MVT::i32, Custom);

Expand Down Expand Up @@ -2637,20 +2636,29 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
SDLoc dl(Op);
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
ARMConstantPoolValue *CPV =
ARMConstantPoolConstant::Create(GV,
UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
bool UseGOT_PREL =
!(GV->hasHiddenVisibility() || GV->isStrongDefinitionForLinker());

MachineFunction &MF = DAG.getMachineFunction();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
EVT PtrVT = getPointerTy(DAG.getDataLayout());
SDLoc dl(Op);
unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(
GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj,
UseGOT_PREL ? ARMCP::GOT_PREL : ARMCP::no_modifier,
/*AddCurrentAddress=*/UseGOT_PREL);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result = DAG.getLoad(
PtrVT, dl, DAG.getEntryNode(), CPAddr,
MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
false, false, 0);
SDValue Chain = Result.getValue(1);
SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
if (!UseGOTOFF)
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
if (UseGOT_PREL)
Result = DAG.getLoad(PtrVT, dl, Chain, Result,
MachinePointerInfo::getGOT(DAG.getMachineFunction()),
false, false, false, 0);
Expand Down Expand Up @@ -2727,29 +2735,6 @@ SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
return Result;
}

SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
SelectionDAG &DAG) const {
assert(Subtarget->isTargetELF() &&
"GLOBAL OFFSET TABLE not implemented for non-ELF targets");
MachineFunction &MF = DAG.getMachineFunction();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
EVT PtrVT = getPointerTy(DAG.getDataLayout());
SDLoc dl(Op);
unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
ARMConstantPoolValue *CPV =
ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
ARMPCLabelIndex, PCAdj);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result =
DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
false, false, false, 0);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
}

SDValue
ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
SDLoc dl(Op);
Expand Down Expand Up @@ -6783,7 +6768,6 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
case ISD::EH_SJLJ_SETUP_DISPATCH: return LowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
Expand Down
1 change: 0 additions & 1 deletion llvm/lib/Target/ARM/ARMISelLowering.h
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Expand Up @@ -514,7 +514,6 @@ namespace llvm {
SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
SelectionDAG &DAG,
TLSModel::Model model) const;
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Expand Down
70 changes: 0 additions & 70 deletions llvm/lib/Target/ARM/ARMInstrInfo.cpp
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Expand Up @@ -132,73 +132,3 @@ void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
AddDefaultPred(MIB);
}

namespace {
/// ARMCGBR - Create Global Base Reg pass. This initializes the PIC
/// global base register for ARM ELF.
struct ARMCGBR : public MachineFunctionPass {
static char ID;
ARMCGBR() : MachineFunctionPass(ID) {}

bool runOnMachineFunction(MachineFunction &MF) override {
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
if (AFI->getGlobalBaseReg() == 0)
return false;
const ARMSubtarget &STI =
static_cast<const ARMSubtarget &>(MF.getSubtarget());
// Don't do this for Thumb1.
if (STI.isThumb1Only())
return false;

const TargetMachine &TM = MF.getTarget();
if (TM.getRelocationModel() != Reloc::PIC_)
return false;

LLVMContext *Context = &MF.getFunction()->getContext();
unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
unsigned PCAdj = STI.isThumb() ? 4 : 8;
ARMConstantPoolValue *CPV = ARMConstantPoolSymbol::Create(
*Context, "_GLOBAL_OFFSET_TABLE_", ARMPCLabelIndex, PCAdj);

unsigned Align =
MF.getDataLayout().getPrefTypeAlignment(Type::getInt32PtrTy(*Context));
unsigned Idx = MF.getConstantPool()->getConstantPoolIndex(CPV, Align);

MachineBasicBlock &FirstMBB = MF.front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
unsigned TempReg =
MF.getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
unsigned Opc = STI.isThumb2() ? ARM::t2LDRpci : ARM::LDRcp;
const TargetInstrInfo &TII = *STI.getInstrInfo();
MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), TempReg)
.addConstantPoolIndex(Idx);
if (Opc == ARM::LDRcp)
MIB.addImm(0);
AddDefaultPred(MIB);

// Fix the GOT address by adding pc.
unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
Opc = STI.isThumb2() ? ARM::tPICADD : ARM::PICADD;
MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
.addReg(TempReg)
.addImm(ARMPCLabelIndex);
if (Opc == ARM::PICADD)
AddDefaultPred(MIB);

return true;
}

const char *getPassName() const override {
return "ARM PIC Global Base Reg Initialization";
}

void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
MachineFunctionPass::getAnalysisUsage(AU);
}
};
}

char ARMCGBR::ID = 0;
FunctionPass *llvm::createARMGlobalBaseRegPass() { return new ARMCGBR(); }
3 changes: 1 addition & 2 deletions llvm/lib/Target/ARM/ARMMachineFunctionInfo.cpp
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Expand Up @@ -20,5 +20,4 @@ ARMFunctionInfo::ARMFunctionInfo(MachineFunction &MF)
RestoreSPFromFP(false), LRSpilledForFarJump(false),
FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0),
PICLabelUId(0), VarArgsFrameIndex(0), HasITBlocks(false),
GlobalBaseReg(0) {}
PICLabelUId(0), VarArgsFrameIndex(0), HasITBlocks(false) {}
10 changes: 1 addition & 9 deletions llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
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Expand Up @@ -110,11 +110,6 @@ class ARMFunctionInfo : public MachineFunctionInfo {
/// pass.
DenseMap<unsigned, unsigned> CPEClones;

/// GlobalBaseReg - keeps track of the virtual register initialized for
/// use as the global base register. This is used for PIC in some PIC
/// relocation models.
unsigned GlobalBaseReg;

/// ArgumentStackSize - amount of bytes on stack consumed by the arguments
/// being passed on the stack
unsigned ArgumentStackSize;
Expand All @@ -133,7 +128,7 @@ class ARMFunctionInfo : public MachineFunctionInfo {
FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
GPRCS1Size(0), GPRCS2Size(0), DPRCSAlignGapSize(0), DPRCSSize(0),
NumAlignedDPRCS2Regs(0), PICLabelUId(0),
VarArgsFrameIndex(0), HasITBlocks(false), GlobalBaseReg(0) {}
VarArgsFrameIndex(0), HasITBlocks(false) {}

explicit ARMFunctionInfo(MachineFunction &MF);

Expand Down Expand Up @@ -204,9 +199,6 @@ class ARMFunctionInfo : public MachineFunctionInfo {
bool hasITBlocks() const { return HasITBlocks; }
void setHasITBlocks(bool h) { HasITBlocks = h; }

unsigned getGlobalBaseReg() const { return GlobalBaseReg; }
void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }

void recordCPEClone(unsigned CPIdx, unsigned CPCloneIdx) {
if (!CPEClones.insert(std::make_pair(CPCloneIdx, CPIdx)).second)
llvm_unreachable("Duplicate entries!");
Expand Down
3 changes: 0 additions & 3 deletions llvm/lib/Target/ARM/ARMTargetMachine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -362,9 +362,6 @@ bool ARMPassConfig::addPreISel() {

bool ARMPassConfig::addInstSelector() {
addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));

if (TM->getTargetTriple().isOSBinFormatELF() && TM->Options.EnableFastISel)
addPass(createARMGlobalBaseRegPass());
return false;
}

Expand Down
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