Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process
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May 5, 2022
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ic-design-project
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Wa'el Engineering Project Repository
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Jun 1, 2024 - Python
This system manages ALU and register file operations based on commands received via UART RX. It operates across two clock domains—one for general processing and another for UART communication. Key functions include executing arithmetic, logic, and data synchronization tasks, with results sent back through UART TX
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Aug 16, 2024 - SystemVerilog
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