2019-02-02 [1.42 Bld 142]

- Addition : Added Parallax SX20/28 target

- Bugfix : Fix some errors regarding escaped characters in quoted sections

- Bugfix : Allow index register scaling for Coldfire (again)

- Bugfix : Better handling of forward-defined displacements on 68K/Coldfire

2019-01-03 [1.42 Bld 141]

- Addition : Added Coldfire target MCF51QM

2018-12-21 [1.42 Bld 140]

- Addition : support Fairchild F8

- Addition : allow < and > modifiers on MCS-96 to force short resp.

long address coding

- Addition : allow < and > modifiers on C16x to force short resp.

long coding

- Change : remove limit of 20 instruction arguments

2018-11-26 [1.42 Bld 139]

- Bugfix : allow word size for 68K move-to-CCR

- Change : regard address space limit for short addressing on 68K

- Bugfix : several fixes regarding forward references for 68K

2018-11-02 [1.42 Bld 138]

- Addition : new command line swith -maxerrors to allow termination

of assembly after a given number of errors.

- Addition : new command line switch -Werror to treat warnings as

errors

- Bugfix : correct value range of 68K MOVEQ instruction

- Addition : allow bit-addressable locations to be written in

internal representation for 80C16x

- Addition : reworked and extended ColdFire support

2018-09-04 [1.42 Bld 137]

- Change : Huge internal reworks to allow reporting column of error

2018-08-06 [1.42 Bld 136]

- Addition : allow nested use of PHASE and DEPHASE

- Addition : allow some pseudo-ops and aliases for operators/phases for 53C8XX

- Bugfix : fix assembly of 8086 OUT <imm>,AX/AL

- Bugfix : fix assembly of 78K4 CALLF/CALLT/RETCS with !-marked argument

- Bugfix : fix assembly of DSAREL() expressions on 53C8xx

- Bugfix : fix specification of data register as 68K PMMU function code

2018-06-18 [1.42 Bld 135]

- Bugfix : some instructions no longer worked on 68008

- Change : P2HEX and P2BIN by default use auto-ranging

2018-05-06 [1.42 Bld 134]

- Addition : add support NXP S12Z ("MagniV") family

2018-04-18 [1.42 Bld 133]

- Change : ALIGN uses execution instead of load address as base

- Addition : allow ALIGN to optionally fill padding area with

byte pattern

2018-04-10 [1.42 Bld 132]

- Bugfix : correct result of strstr() if search string is at end

of string

- Bugfix : correct month display on locale systems (off-by-one)

- Bugfix : Also regard ' and " if enclosed in () or []

2018-03-29 [1.42 Bld 131]

- Bugfix : correct date display on locale systems

2018-03-28 [1.42 Bld 130]

- Bugfix : clean up date & time format handling for locale-based systems

2018-03-16 [1.42 Bld 129]

- Bugfix : correct assumption of length of forward JSR/JMP on 68HC12

2018-03-11 [1.42 Bld 128]

- Bugfix : correct distance range checking on SC/MP

2018-03-04 [1.42 Bld 127]

- Bugfix : avoid 'target not on same page' for forward references

on several platforms

2018-02-28 [1.42 Bld 126]

- Addition : add AT43USB355

- Bugfix : when writing line to .i file that contained a macro

call and a label, only write out the label, plus an

eventual comment.

2018-02-24 [1.42 Bld 125]

- Bugfix : correct argument checking for CHARSET

- Bugfix : If a line calling a macro contains a label not consumed

by the macro, output the line (minus tha macro call)

in the -P output

- Addition : Optionally display column and position in source line

for some errors

2018-01-21 [1.42 Bld 124]

- Addition : add ATmega{8|16|32}U2,

ATmega{16|32}U4,

ATmega32U6,AT90USB646/647,AT90USB1286/1287

- Bugfix : correct address space deduction for AVR

- Bugfix : defining CPU aliases for AVR works again

2017-12-26 [1.42 Bld 123]

- Addition : add ATtiny48/88/43u/441/841/828/1634/87/167/

4/5/9/10/20/40/102/104/28/11/12/15/13A/24A/44A/

84A, AT90S2323/2333/2343/8534

- Addition : replace MACEXP with MACEXP_DFT/MACEXP_OVR

2017-11-27 [1.42 Bld 122]

- Bugfix : correct double ASSR definition for ATmega8/16/32

- Bugfix : correct UPE definition for ATmega162

- Bugfix : correct SFR area size for ATmega1284RFR2

- Addition : add a first batch of ATtiny variants

2017-11-21 [1.42 Bld 121]

- Bugfix : correct behaviour of DATA for Atmel AVR

2017-11-20 [1.42 Bld 120]

- Addition : add more ATmega variants

- Addition : more flexible usage of ENUMs

- Addition : if a statement was called with an incorrect number of

arguments, the allowed range is printed as extended

error message

- Addition : if a statement or addressing mode is not supported on

the selected CPU, the CPU variants supporting it are

listed as extended error message

- Addition : if an ENDM statement is missing, print which type of

statement (macro defintion, REPT, IRP(C), WHILE) lacks

an ENDM.

2017-08-21 [1.42 Bld 119]

- Addition : add NEC 78K4

- Addition : add Siemens SAB 80C382

- Addition : add OKI MCS-48 variants

2017-07-30 [1.42 Bld 118]

- Bugfix : correct several flaws in 68K address mode decoder

2017-06-28 [1.42 Bld 117]

- Bugfix : correct MSP430 source operand conversion 0(Rn) -> @Rn

- Addition : add HuC6280 target

- Addition : add 65C19 target

- Addition : allow IXH/IYH as alias for IXU/IYU on Z80UNDOC

- Addition : allow SLS as alias for SLIA on Z80UNDOC

2017-06-03 [1.42 Bld 116]

- Addition : add W65C02S target (proposed by Alessandro Gatti)

- Change : implement MSP430 emulated instructions within assembler instead

of with macros

- Addition : add MSP430X instruction set

- Addition : allow more fine-grained control of macro expansion in listing

- Bugfix : allow searching PATH variables longer than 255 characters

- Bugfix : use correct character on Windows platforms to concatenate

AS_MSGPATH and message file name

2017-02-26 [1.42 Bld 115]

- Addition : allow alternate syntax for SET and EQU

- Addition : support the MICO8 prom_init hex format in P2HEX

- Bugfix : handle the return value of fgets() and getcwd() at some places

to silence compiler warnings

- Bugfix : correct handling of SCAL instruction for 1805(A)

- Addition : differentiate 1804/1805/1806 and 1804A/1805A/1806A instruction

set

2016-11-01 [1.42 Bld 114]

- Addition : add support for OKI OLMS-40

- Addition : allow some alternate notations for 78C1x indirect addressing

- Addition : add support for MIL STD 1750

- Addition : allow Z80-style syntax for 8080/8085

- Addition : add support for Hitachi HMCS400

2016-09-25 [1.42 Bld 113]

- Addition : added bit definitions for 80C320 second UART

- Bugfix : fix memory leak and incorrect format string on DPMI version

- Bugfix : fix a couple of memory handling errors detected by valgrind

2016-09-11 [1.42 Bld 112]

- Addition : add support for Toshiba TC9331

- Addition : add support for TI TMS 320C4x

- Addition : add include file with Hitachi/Renesas 6303 registers

2016-08-21 [1.42 Bld 111]

- Bugfix : correct a couple of bugs detected by CLang

- Addition : add support for NEC 78K3

2016-07-01 [1.42 Bld 110]

- Addition : allow enforcement of prefixes for TLCS-9000

2016-06-26 [1.42 Bld 109]

- Bugfix : Correct output file in respect to expanded structures

2016-04-26 [1.42 Bld 108]

- Bugfix : For 8080/8085, complain about wrong register names

for PUSH/POP

- Addition : Allow automatic 16/32-bit deduction for inner

displacement on 68K

- Addition : Allow Intel-style hex syntax for addresses passed

to P2BIN and P2HEX

2016-02-07 [1.42 Bld 107]

- Addition : Allow register symbols on MCS-48/(2)51

2015-10-28 [1.42 Bld 106]

- Addition : Allow sub-structures of same name in different structures

2015-10-23 [1.42 Bld 105]

- Bugfix : Correct Handling of nested structures and unions

- Addition : Allow unnamed structures and unions

- Bugfix : Correct some SFR definitions for DS80C320

- Addition : Allow ? as argument to BYT/FCB/ADR/FDB to reserve space

2015-10-17 [1.42 Bld 104]

- Bugfix : Correct SHARED symbol output in C mode

- Bugfix : Correct coding of CC on 6809 for push/pull

2015-09-26 [1.42 Bld 103]

- Bugfix : On 8008, the assembler accidentally allowed

INR, DCR and MOV with invalid register operands.

2015-08-30 [1.42 Bld 102]

- Bugfix : yet another fix to correct handling of BSR

on 68K

2015-08-19 [1.42 Bld 101]

- Bugfix : correct PC-relative addressing on 807x target

- Bugfix : add missing condition codes of 68K FPU

- Bugfix : correct handling of 68K BSR instruction with

8 bit displacement

2015-08-17 [1.42 Bld 100]

- Bugfix : default integer constant mode for INS807x was

Intel and not C as documented

- Bugfix : various fixes & extensions for 807x target

2015-08-07 [1.42 Bld 99]

- Bugfix : Correct handling of variadic macros

- Bugfix : Suppress detection of 0x... as floating

point constant on some platforms

2015-05-25 [1.42 Bld 98]

- Addition : Add TMS1000 target

2014-12-20 [1.42 Bld 97]

- Bugfix : repair -cpu command line option that was broken in previous build

2014-12-07 [1.42 Bld 96]

- Change : rework/cleanup PIC, 1802, 3201x, 3202x, 3203x, 3206x, 3254x,

4004, MELPS4500, 47Cxx, MCS-48/51, 56K, PowerPC, 65xx, 68xx, 68K targets

- Addition : Add TLCS-870/C target

- Bugfix : correct handling of TLCS-870 JR instruction without condition

2014-09-21 [1.42 Bld 95]

- Change : flip order of changelog

- Change : rework/cleanup 75K0, SH, 80C16x targets

- Addition : allow keyword arguments and parameter defaults for macros

2014-08-31 [1.42 Bld 94]

- Bugfix : for Z80 target, detect invalid condition identifiers

- Bugfix : avoid infinite loop on M16 when chained addressing is used incorrectly

- Change : rework/cleanup COP8, AVR, ACE, TMS9900, TLCS/9000, TLCS/900, i960,

MCS-96, TLCS/90, 8X30x, TLCS/870, 8086, 8085, 78Kx, 78c10, uPD77230, uPD772x,

65816/7700 targets, complete reworks and testcase on M16

- Bugfix : BCLR/BSET/BSETI/BTST on M16 use format G/E/Q instead of G/E/R

- Bugfix : do not allow JSR with direct mode on 6800

- Bugfix : correct 8087 FIMUL coding

- Bugfix : correct JSL/JML byte order for 65816

- Bugfix : correct COP, PEI, PEA, BIT instructions for 65816

- Bugfix : use correct bank register for 65816 JMP/JSR instruction

- Addition : on 65816, allow DBR as alias for DT and PBR as alias for PG

2014-06-19 [1.42 Bld 93]

- Change : put entry address into 01 record for Intel8 hex format

- Bugfix : correct uninitialized array in M16 decoder

- Change : for Z80, do not warn about possible short addressing for

RL/RLC/RR/RRC A

- Change - rework/cleanup Z80, F2MC8L, Picoblaze, H8/300, XA, M16C, STx

targets, partially rework and provide initial test case for

M16 target

2014-03-08 [1.42 Bld 92]

- Bugfix : correct handling of escaped quotation marks when converting string

to uppercase

- Addition : add RORG statement

- Change : for unresolved forwards, put forward statement position into extended error

- Addition : added new function ASSUMEDVAL to query values set via ASSUME

2014-03-03 [1.42 Bld 91]

- Change : allow register names R10...R15 for 4004/4040

- Addition : add COP444 target

2013-12-21 [1.42 Bld 90]

- Bugfix : IRPC messed up local symbol handling

- Bugfix : correct handling of escaped quotes in string constants

- Change : allow up to 64K code per line

2013-08-07 [1.42 Bld 89]

- Bugfix : PADDING instruction available for 6805/6808

- Addition : add COP440 target

- Bugfix : better handling of overlong souce code lines

2013-03-22 [1.42 Bld 88]

- Addition : support 75xx instruction set A & B

2013-03-09 [1.42 Bld 87]

- Bugfix : correct PC-relative addressing on SC/MP

- Addition : (NO)GLOBALSYMBOLS parameter for macros

- Addition : add support for NEC uPD75xx

2012-12-31 [1.42 Bld 86]

- Change : add Dx pseudo instructions to Signetics 2650

2012-12-09 [1.42 Bld 85]

- Change : allow register symbols for Zilog Z8

2012-09-02 [1.42 Bld 84]

- Addition : add support for XMOS XS1

- Addition : optionally support UTF8 encoding

- Addition : add Makefile definitions for OSX

2012-05-26 [1.42 Bld 83]

- Change : implicit macro parameters are always case-insensitive

- Addition : add REG instruction to MSP430

2012-01-21 [1.42 Bld 82]

- Addition : added support for MPC 821 from Marcin Cieslak

- Bugfix : regard symbol name expansion in arguments for SHARED

2011-10-20 [1.42 Bld 81]

- Change : range checking of RP value for Z8 more graceful

2011-08-01 [1.42 Bld 80]

- Change : rework (e)Z8 working register addressing

2010-12-12 [1.42 Bld 79]

- Bugfix : correct back-transformation of SFR addresses to absolute for 80C167

- Bugfix : allow arbitrary values for register pointer on eZ8

- Change : split up Mico8 variants

2010-06-14 [1.42 Bld 78]

- Bugfix : do not optimize out 68K BSR if it has zero distance

2010-04-17 [1.42 Bld 77]

- Bugfix : address problem of overlapping strcpy()

2010-04-11 [1.42 Bld 76]

- Bugfix : correct operand checking for SHA/SHL on M16C

2010-03-26 [1.42 Bld 75]

- Bugfix : correct address range for M16C bit short addressing

2010-03-14 [1.42 Bld 74]

- Addition : DW/DD/DQ/DD, DC.[wlxsdp], ADR also accept string arguments

2010-02-27 [1.42 Bld 73]

- Bugfix : corrected P2BIN checksum generation on Win32 systems

- Bugfix : corrected macro nesting dispay in listing

2010-01-01 [1.42 Bld 72]

- Bugfix : corrected address offset handling for H8/500

- Bugfix : some coding corrections for Lattice Mico8

2009-07-25 [1.42 Bld 71]

- Bugfix : corrected H8/500 register-to-register MOV coding

2009-06-07 [1.42 Bld 70]

- Addition : added named temporary symbols

2009-05-10 [1.42 Bld 69]

- Bugfix : allow more CPU aliases

- Addition : dispay macro nesting in listing

2009-04-13 [1.42 Bld 68]

- Bugfix : correct SC/MP relative addressing regarding page wrap

2009-04-10 [1.42 Bld 67]

- Bugfix : correct AVR branch instructions when target is beyond 64K

2009-02-08 [1.42 Bld 66]

- Bugfix : correct DINT coding for TMS7xxx

2008-11-23 [1.42 Bld 65]

- Addition : allow Q for octal constants in Intel mode

- Bugfix : correct coding of OUT instruction for 8008

- Change : allow NUL characters in string symbols (again)

2008-10-25 [1.42 Bld 64]

- Addition : added CHARFROMSTR function

2008-08-29 [1.42 Bld 63]

- Bugfix : correct 68K TST addressing modes, PC-relative offsets for a few instructions

2008-08-22 [1.42 Bld 62]

- Bugfix : correct MCS-96 DPTS/EPTS coding

2008-08-17 [1.42 Bld 61]

- Bugfix : correct MCS-96 BMOVI coding

- Bugfix : correct definition of PORTQS for MC68332

2008-08-10 [1.42 Bld 60]

- Bugfix : allow 68xxx dynamic FMOVEM register list with lowercase-written data register

- Bugfix : correct addressing mode list for FMOVEM register-to-memory

- Change : allow 68K bit instructions with arguments ranging from 0..255 and issue

warning for numbers beyond operand length

2008-06-22 [1.42 Bld 59]

- Addition : add Atari Asteroids vector processor as target

- Bugfix : disallow 68xxx byte-size ADDQ/SUBQ when using an address register

2008-03-31 [1.42 Bld 58]

- Bugfix : correct 8086 CALLF/JMPF instructions

2007-12-31 [1.42 Bld 57]

- Bugfix : correct SKINT -> SKNIT on 78C1x

- Bugfix : correct LDN and RLDI instructions for 180x

- Change : MSP decoder now works with hash table

- Addition : add some MSP430 bit definitions

2007-09-24 [1.42 Bld 56]

- Bugfix : correct handling of minus operator in nested expressions

2007-05-01 [1.42 Bld 55]

- Bugfix : set correct default maximum nesting level

- Addition : add BANKSEL pseudo instruction for PIC16C8x

- Addition : add optional new integer syntax

2006-12-19 [1.42 Bld 54]

- Bugfix : -t option allows full range of list mask

- Bugfix : correct output of Intel16/Intel32 hex format for

word-addressed targets

2006-12-17 [1.42 Bld 53]

- Bugfix : corrected address space assignment of ATmega128

- Bugfix : fixed negative assembly times on Win32

2006-12-09 [1.42 Bld 52]

- Bugfix : added missing instructions for 78K2 target

- Bugfix : corrected some instruction codings for 78K0

2006-08-26 [1.42 Bld 51]

- Addition : finished 8008 target

2006-08-05 [1.42 Bld 50]

- Addition : Add (68)RS08 (contribution by Andreas Bolsch)

- Bugfix : For AVR, add the ATmega variant of the LPM instruction

- Addition : Add AVR targets & address spaces up to ATmega256

- Bugfix : correct parsing of indexed expressions for Z80 and TLCS-90(0)

2006-06-24 [1.42 Bld 49]

- Addition : Add (68)HCS12 target

2006-05-08 [1.42 Bld 48]

- Bugfix : add range checks to arguments on some COP41x instructions

- Addition : Add COP42x target

2006-04-15 [1.42 Bld 47]

- Addition : Add ${PREFIX} to installation script

2006-04-07 [1.42 Bld 46]

- Bugfix : remove some warnings around paged address space of 68HC12X

- Addition : Add COP4 target

2006-04-04 [1.42 Bld 45]

- Bugfix : some corrections around paged address space of 68HC12X

2006-03-18 [1.42 Bld 44]

- Addition : Add paged address space for 68HC12X

2005-12-17 [1.42 Bld 43]

- Bugfix : XGDX instruction did not work on 6301

- Addition : Add 2650 target

- Bugfix : listing on 16-bit hosts lead to crashes

2005-11-04 [1.42 Bld 42]

- Addition : warn about MSP430 code on odd addresses

- Bugfix : .b as length specifier for 68K branch instructions would not work

- Bugfix : correct address field of MOS hex format

- Bugfix : correct DUP detection in Intel-style data disposition

instructions

2005-10-02 [1.42 Bld 41]

- Bugfix : correct endinaness for constant disposition on XGATE

- Bugfix : correct endinaness for constant disposition of 8-bit Motorola ops

on big-endian platforms

- Bugfix : allow arbitrary register names for KCPSM3

- Bugfix : correct register naming for KCPSM3

2005-09-17 [1.42 Bld 40]

- Bugfix : correct 68HC12 behaviour for forward jump/call instructions

- Addition : allow .w and .b as length specifier for 68K branch instructions

2005-09-12 [1.42 Bld 39]

- Addition : add HC12X/XGATE instruction extensions

2005-09-08 [1.42 Bld 38]

- Bugfix : correct Qxxn register decoding on TLCS-900

2005-08-07 [1.42 Bld 37]

- Bugfix : correct mnemonic conflict for EXPORT on MICO8

- Addition : allow instruction aliases for ...I variants on MICO8

2005-08-06 [1.42 Bld 36]

- Addition : added LatticeMico8

2005-03-21 [1.42 Bld 35]

- Addition : added ATM & LDWX instructions for Zilog eZ8

- Addition : added KCPSM3 core

2004-11-20 [1.42 Bld 34]

- Bugfix : allow double-memory addressing variants on TLCS/900 again

2004-09-26 [1.42 Bld 33]

- Bugfix : correct operation of INHX... modes in P2HEX

- Bugfix : setting of entry address in P2BIN did not work

- Bugfix : fix crashes when programs defined more than 256

bytes of code in one line

2004-05-29 [1.42 Bld 32]

- Bugfix : correct erroneous detection of DUP operator inside

string/character constants

2004-03-31 [1.42 Bld 31]

- Bugfix : corrected 68HC11K4 instruction set, PRWINS command

2003-12-07 [1.42 Bld 30]

- Addition : added NEC 78K2

2003-08-17 [1.42 Bld 29]

- Addition : added 80C251T SFRs

- Addition : added 80C167CS SFRs

- Addition : added Zilog eZ8

2003-05-25 [1.42 Bld 28]

- Addition : added 4040 machine instructions

2003-03-30 [1.42 Bld 27]

- Addition : integrated support for KCPSM/PicoBlaze provided by Andreas

Wassatsch

- Addition : added support for the INS807x processor family

- Bugfix : allow source file specification in key file

2003-02-26 [1.42 Bld 26]

- Bugfix : symbolic displacement with Atmel AVR did not work any more

2003-02-02 [1.42 Bld 25]

- Extension : added EXPRTYPE function

- Bugfix : in case-sensitive mode, IRP arguments were converted

to uppercase

- Bugfix : 4004 JCN instruction did not allow multiple conditions

- Extension : allow line continuation

2002-11-23 [1.42 Bld 24]

- Extension : added undocumented 8085 instructions

- Extension : improved structure handling, added unions

- Extension : DC allows ? as operand

2002-10-11 [1.42 Bld 23]

- Bugfix : repaired named temporary symbols

2002-10-09 [1.42 Bld 22]

- Extension : added nameless temporary symbols

2002-05-25 [1.42 Bld 21]

- Extension : added Atmel MEGA8/MEGA16 CPU types & registers

- Bugfix : data disposal for Atmel did not work correctly

- Extension : extended the 320C6x target with pseudo instructions and

machine instructions that previously had to be emulated

with macros

- Extension : ENDIF/ENDCASE show the line number of the IF/CASE statement

they were matched to in the listing

- Bugfix : [] as specifier for the root section was not accepted

- Bugfix : avoid incorrect debug output when addresses of sections vary

2002-03-10 [1.42 Bld 20]

- Bugfix : corrected line counting behaviour when REPT/IRP/WHILE draw

contents not from file

- Extension : more precise error messages for type conflicts in some places

2002-01-27 [1.42 Bld 19]

- Bugfix : BIT-statements inside macros did not work correctly

- Bugfix : WHILE-statement evaluates condition after last statement

2002-01-13 [1.42 Bld 18]

- Extension : added INTLABEL option for macros

2001-11-04 [1.42 Bld 17]

- Extension : added -gnuerrors command line option

- Extension : added support for the TMS320C54x family from Texas Instruments

2001-08-11 [1.42 Bld 16]

- Bugfix : do not allow line debug info in pseudo segments

- Bugfix : more secure detection of ASCII integer constants

[1.42 Bld 15]

- Bugfix : fixed extended register coding for TLCS-900

- Bugfix : P2HEX: fix specification of entry address on command line

[1.42 Bld 14]

- Bugfix : fixed crashes when HC16 cpu type was set from command line

[1.42 Bld 13]

- Bugfix : in der Kommandozeile angegebene Symbole wurden immer in

Großbuchstaben umgewandelt

- Erweiterung : unterstützt 68HC11K4 windowing

- Bugfix : pbind verfälschte sporadisch Daten beim Umkopieren

- Erweiterung : added avrlen parameter to p2hex

- Bugfix : on DOS platforms, PLIST did not display 32-bit-addresses

incorrectly

[1.42 Bld 11]

- Bugfix : 6809-PUSH/PULL mit D-Register klappt jetzt wirklich (sorry!)

- Bugfix : ACE: Segmente vereint, Bereiche/Startadressen korrigiert

[1.42 Bld 10]

- Erweiterung : NoICE-Symboltypenmaske setzbar

- Bugfix : 6809-Stackoperation mit anderem Stackpointer funktionierten

nicht

- Erweiterung : PUSH/PULL 6809 funktionieren auch mit Register D=A+B

- Bugfix : 8048-ORL/ANL funktionieren wieder mit p1/p2

[1.42 Bld 9]

- Bugfix : 680x0-Adressierungen korrigiert

äußeres Displacement jetzt auch in Klammer schreibbar

[1.42 Bld 8]

- Erweiterung : DC.x / DS.x funktionieren auch für 68HC16

- Änderung : Lizenz jetzt GPL

[1.42 Bld 7]

- Bugfix : / als Parameterzeichen funktioniert wieder

[1.42 Bld 6]

- Bugfix : Kodierungsfehler TLCS-900(MINC/MDEC, BS1B/BS1F) behoben

- Bugfix : Abstürze bei BINCLUDE größerer Dateien unter DPMI behoben

[1.42 Bld 5]

- Bugfix : REPT/IRP(C)/WHILE-Statement in IF-geklammerten Zweigen werden komplett

übersprungen

- Bugfix : Adressen NoICE-Debugfiles werden jetzt als Hex ausgegeben und auch so

gekennzeichnet

- Erweiterung : die maximale Verschachtelungstiefe für Aufrufe eines Makros ist jetzt auf

einen per NESTMAX einstellbaren Wert begrenzt

- Bugfix : weitere Fixes in Bankregister-Parser TLCS-900

2000-05-29 [1.42 Bld 4]

- Erweiterung : Packing-Befehl für AVR eingeführt

- Erweiterung : ALLARGS/ARGCOUNT für Makros

- Bugfix : Bankregister-Parser TLCS-900 repariert

- Erweiterung : temporäre Symbole

2000-03-13 [1.42 Bld 3]

- Bugfix : 'ambiguous' Warnungen bei egcs beseitigt

- Bugfix : EXG beim 680x0 korrigiert

- Aenderung : Adressraum des 68HC08 ist jetzt 64K

2000-02-13 [1-42 Bld 2]

- Bugfix : ADDX/SUBX beim 68000 waren vertauscht

2000-01-09 [1.42 Bld 1]

- Bugfix : ADDX/SUBX beim 68000 funktionierten nicht

- Bugfix : Im Listing und bei P2BIN/P2HEX/PBIND waren noch einige

Formatstrings nicht plattformabhängig, was bei Werten über

32K merkwürdige Effekte ergab...

- Bugfix : PC-relative Adressierung für 56300 benutzte falschen Offset

- Erweiterung : Längenoptionierung bei absoluter Adressierung im 56xxx

läßt sich per '>' ausschalten

1999-09-15 [1.41r8 Bld 15]

- Erweiterung : Fairchild ACE als Prozessorziel

- Bugfix : Probleme mit dem NULL-Device und dem NLS-Support einiger Linux-

Distributionen behoben

- Erweiterung : REG-Statement fuer PowerPCs

- Bugfix : Registerpaarsyntax fuer 4004 korrigiert

- Erweiterung : Minimalrecordlaenge fuer P2HEX

1999-07-06 [1.41r8 Bld 14]

- Erweiterung : Unterstützung der TMS320C20x-Befehlsuntermenge

- Erweiterung : hexadezimale Adressangaben für die Hilfsprogramm können jetzt

auch in C-Notation gemacht werden

- Erweiterung : OUTRADIX-Befehl

- Änderung : Syntax für 4004-Registerpaare ist jetzt R[02468ABCE]R[13579BDF]

- Erweiterung : Unterstützung Fujitsu F²MC8L

- Bugfix : FMOVE <ea>,FPm funktionierte mit <ea> = D1 nicht (680x0)

- Bugfix : FSMOVE und FDMOVE fuer 68040 fehlten noch

- Erweiterung : Kommandozeilenoption für P2HEX, um Minimalgröße S-Records zu

setzen

- Bugfix : -l - Option in P2HEX funktionierte nicht

1999-05-02 [1.41r8 Bld 13]

- Erweiterung : WRAPMODE-Befehl fuer Atmel AVR

- Änderung : In Atmel-Debugfiles wird für jedes Wort eines Maschinenbefehls ein

Record geschrieben, nicht mehr nur für das erste

1999-04-20 [1.41r8 Bld 12]

- Bugfix : Parameterbereich B_RST für Ziel SC14xxx falsch

1999-04-09 [1.41r8 Bld 11]

- Erweiterung : Befehle / Register PPC403-MMU

- Erweiterung : National SC144xx-Support

- Bugfix : Angabe von Symbol-Defines in der Kommandozeile, die nicht

einfache Konstanten sind, konnten zu Abstürzen führen