This is a logic analyzer that implements extended SUMP protocol for RP2040.
- 16 channels
- 200MHz sample rate
- 100K samples
- 1K pre trigger samples
- Level and edge triggers
- Up to 4 triggers (1 stage)
- RLE implemented
Upload the binary.
Connect to a SUMP client:
- Pulseview(1)(2).
- Sigrok-cli
- Jlac.
(1) Libsigrok has a bug when reading from device. Maximum sample rate and maximum sample size in Pulseview selection lists are incorrect. See fork which fixes the issue.
(2) Sump protocol does not have trigger types and libsigrok sends first stage triggers only. Use GPIO config to select trigger type for Pulseview.
16 channels are available on GPIOs 0 to 15.
If enabled, debug output is on GPIO 16 at 115200bps.
Use GPIOs 18 and 19 to configure the device at boot. See configuration.
Default trigger type is trigger edge. To select trigger level, see configuration.
Four triggers can be enabled. Additional triggers will be ignored.
Led blinks at boot and during the capture process.
Upload the binary to the RP2040. Drag and drop logic_analyzer.uf2.
To connect to Pulseview:
- Open dialog Connect to device.
- Select Openbench Logic Sniffer & SUMP compatibles (ols).
- Select Serial interface.
- Click on Scan for devices and accept.
RLE can be enabled in Device configuration dialog:
GPIOs 18 and 19 are used to configure the device at boot.
Connect GPIOs to ground to enable/select.
Trigger type
Sump protocol has one trigger type and Pulseview sends first stage triggers only.
GPIO 19 to GND: triggers based on stages (triggers from Pulseview are level triggers). If not grounded, all are edge triggers.
Debug mode
GPIO 18 to GND: enable debug mode. Debug output is on GPIO 16 at 115200 bps.
If no GPIO is grounded, the default configuration is:
- Trigger edge override: enabled.
- Debug mode: disabled.