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Prepare first release

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Overdue by 4 year(s)
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Due by Jul 31, 2020•
Last updated May 18, 2023
82% complete

Merge uploaded and reviewed interfaces to 'release' branch. This should also include a basic documentation and offline compiler checks.

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0 issues of 3 selected

  • Define tests for the interfaces

    Discussion
    Testbench
    Status: Open.
    #9 In VHDL/Interfaces;
    · Paebbels opened on Jul 4, 2020

  • Naming Methodology

    Discussion
    EnhancementNew feature or request
    Status: Open.
    #10 In VHDL/Interfaces;
    · JimLewis opened on Jul 4, 2020

  • Should we use std_logic or std_ulogic?

    Discussion
    EnhancementNew feature or request
    Status: Open.
    #13 In VHDL/Interfaces;
    · Paebbels opened on Jul 4, 2020
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