The purpose of this issue is to ask the community what alternative naming to master/slave can be used in this repo and in other libraries projects related to VHDL. There have been multiple proposals, and some other languages have already made the change. However, in VHDL it seems that many terms are usable in specific domains but not generic enough. At the same time, some other terms are too generic, and the meaning of the relation between modules/components/agents in the system might be lost.

I gathered multiple terms in the table below. I'd propose people (anyone) to pick a term from the first column (any), and a term from the second column (any). Then, search if masterterm <-> slaveterm has been written below in this issue/thread. If found, react to it. If not found, write a reply/comment which starts with masterterm <-> slaveterm.

To keep this tidy to some extent, anyone is welcome to reply with short and explicit arguments about why some combination is not adequate for some domain. Me or other maintainers will move those arguments to the comment where that combination was proposed. For this reason, authors of the comments (which are to be reacted to) will NOT be responsible for the content. At the same time, please keep the discussions in separate channels. Let's take this as a community effort to build some knowledge.

See also: https://www.theserverside.com/opinion/Master-slave-terminology-alternatives-you-can-use-right-now