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<< /S /GoTo /D (section.1) >>
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(1 Background)
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<< /S /GoTo /D (section.2) >>
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(2 Introduction)
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<< /S /GoTo /D (section.3) >>
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(3 Functional description)
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<< /S /GoTo /D (subsection.3.1) >>
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(3.1 Pinout of size1 module)
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<< /S /GoTo /D (subsection.3.2) >>
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(3.2 Pinout of larger sized modules)
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<< /S /GoTo /D (subsection.3.3) >>
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(3.3 TRAMs with more than one transputer)
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<< /S /GoTo /D (subsection.3.4) >>
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(3.4 Extra pins)
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<< /S /GoTo /D (subsection.3.5) >>
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(3.5 Subsystem signals driven from a TRAM)
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<< /S /GoTo /D (subsection.3.6) >>
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(3.6 Memory parity)
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<< /S /GoTo /D (subsection.3.7) >>
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(3.7 Memory map)
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<< /S /GoTo /D (section.4) >>
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(4 Electrical description)
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<< /S /GoTo /D (subsection.4.1) >>
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(4.1 Link outputs)
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<< /S /GoTo /D (subsection.4.2) >>
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(4.2 Link Inputs)
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<< /S /GoTo /D (subsection.4.3) >>
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(4.3 notError output)
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<< /S /GoTo /D (subsection.4.4) >>
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(4.4 Reset and analyse inputs)
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<< /S /GoTo /D (subsection.4.5) >>
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(4.5 Clock Input)
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<< /S /GoTo /D (subsection.4.6) >>
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<< /S /GoTo /D (subsection.4.7) >>
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(4.7 GND, VCC)
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<< /S /GoTo /D (section.5) >>
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(5 Mechanical description)
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<< /S /GoTo /D (subsection.5.1) >>
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(5.1 Width and length)
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<< /S /GoTo /D (subsection.5.2) >>
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(5.2 Vertical dimensions)
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<< /S /GoTo /D (subsection.5.3) >>
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(5.3 Direction of cooling)
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<< /S /GoTo /D (section.6) >>
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(6 TRAM pins and sockets)
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<< /S /GoTo /D (subsection.6.1) >>
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<< /S /GoTo /D (subsection.6.2) >>
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(6.2 Through-board sockets)
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<< /S /GoTo /D (subsection.6.3) >>
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(6.3 Subsystem pins and sockets)
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<< /S /GoTo /D (subsection.6.4) >>
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<< /S /GoTo /D (section.7) >>
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(7 Mechanical retention of TRAMs)
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<< /S /GoTo /D (section.8) >>
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(8 Profile drawings)
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