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1. MultiCore_L2_Cache MultiCore_L2_Cache Public

   A UVM-based verification environment for a multi-core, write-back L2 cache on 32-bit RISC-V, enforcing MESI coherence with L1 caches and interfacing to DRAM over AXI4-Lite.

   SystemVerilog 2

2. dhruv dhruv Public

   This is my personal website

   HTML

3. dwvshep/A.U.R.A.---FlashAttention-ASIC-Accelerator dwvshep/A.U.R.A.---FlashAttention-ASIC-Accelerator Public

   SystemVerilog based ASIC accelerator for the FlashAttention kernel used in modern transformers

   SystemVerilog 1

4. custom_ip_library custom_ip_library Public

   A collection of reusable, parameterized SystemVerilog RTL IP blocks

   SystemVerilog