There should be support for FPS limiting by integer division (60, 30, 20, 15, 12...).

Proposed Solution

1. Add a clock to the FPGA that outputs "time since reset" to a 4 byte register in ($7000...$7fff).
2. Add a way to read the frame rate limiter from the ROM on reset.
3. In crt0.s, instead of always leaving the interrupt handler on _IN_VBLANK, there should be a check for if enough time has passed.