Synthesizable AXI4 crossbar with a full UVM verification environment — RTL, SVA, coverage, stress, and CI.
Deterministic hardware verification engine that fails CI when connected components violate electrical or interface contracts.
High-performance discrete-time voltage-mode PID controller for a 100 kHz synchronous buck converter implemented on a Xilinx Spartan-7 FPGA. Features parallel hardware execution, 23-bit fixed-point precision, dual-stage saturation, and cycle-accurate verification. Validated on physical hardware.
Wokwi Arduino Uno NTC thermistor temperature validation bench with ADC conversion, Python analysis, plots, and automated PDF reporting.
A deterministic, multi-phase C++ PCIe protocol analyzer for decoding TLP traffic, validating transactions, modeling system behavior, and performing fault injection with cross-domain correlation (PCIe, CXL, NVMe).
A framework that ensures that Nitrux runs in a predictable, supportable, and well-understood environment.
Utility scripts and diagnostics for Arduino boards — modular, reusable, and hardware-focused.
Simulation-only validation ladder for mapping neural weight matrices to HRM-style photonic transfer functions.
Hardware-constrained validation of SRFM metastable structural diagnostics on IBM Quantum systems.
Python tool for parsing memory validation logs and generating clean CSV and Markdown reports for server hardware testing workflows.
Production-style Python automation framework for server hardware & SSD validation | pytest | CI/CD | defect classification | GitHub Actions
Linux hardware preflight: 18 sensor/memory/peripheral checks via /proc, /sys, syscalls, serial I/O — JSON + Markdown reports
Hardware Control GateKeeper Kernels for AI inference within frameworks.
Automated test infrastructure for 6+ power supply topologies. Precision measurement, real-time control, LED monitoring, and MySQL integration. Each test generates QR-code linked quality metrics. Embedded systems & hardware-software integration.
Public-safe embedded hardware, PCB, firmware, breadboard, and validation patterns for intelligent infrastructure.
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