This is a simulator of a CPU implementing the RISC-V RV32I ISA. It was made for the Advanced Computer Architecture (COMS30046) unit at University of Bristol.

• Rust 1.85 & Cargo -- for compiling the simulator
• Docker (optional) -- for compiling example programs

First, clone the repository:

git clone [email protected]:miloszwasacz/cpu-sim.git
cd cpu-sim

Then, to compile test programs, run the Docker image with RISC-V toolchain:

docker compose run --remove-orphans riscv-toolchain

# Inside the docker container, run GNU Make to compile 
# all programs from the `test/res/` directory
make 

exit # Exit the docker container

Lastly, to compile the simulator and run a RISC-V program:

cargo run --release -- "<path-to-riscv-binary>"