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esp32: Support I2S.
Signed-off-by: Vincent1-python <[email protected]>
1 parent b0b1660 commit 06755d9

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Lines changed: 184 additions & 9 deletions

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‎ports/esp32/boards/mpconfigboard_esp32s31_common.cmake‎

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set(IDF_TARGET esp32s31)
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list(APPEND SDKCONFIG_DEFAULTS
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boards/sdkconfig.base
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boards/sdkconfig.s31_base
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boards/sdkconfig.ble
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boards/sdkconfig.spiram_oct
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)

‎ports/esp32/boards/sdkconfig.s31_base‎

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# MicroPython on ESP32, ESP IDF configuration
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# The following options override the defaults
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CONFIG_IDF_FIRMWARE_CHIP_ID=0x0000
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# Compiler options: use -O2 and disable assertions to improve performance
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CONFIG_COMPILER_OPTIMIZATION_PERF=y
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CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE=y
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# Application manager
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CONFIG_APP_EXCLUDE_PROJECT_VER_VAR=y
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CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR=y
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# Bootloader config
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CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
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CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y
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CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE=y
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# Change default log level to "ERROR" (instead of "INFO")
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CONFIG_LOG_DEFAULT_LEVEL_ERROR=y
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# Set the maximum included log level higher than the default,
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# so esp.osdebug() can enable more logging at runtime.
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#
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# To increase the max log verbosity to Debug or Verbose instead, comment
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# CONFIG_LOG_MAXIMUM_LEVEL_INFO=y and uncomment one of the other settings.
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#
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# If not needed, the next line can be commented entirely to save binary size.
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CONFIG_LOG_MAXIMUM_LEVEL_INFO=y
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#CONFIG_LOG_MAXIMUM_LEVEL_DEBUG=y
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#CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE=y
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# Main XTAL Config
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# Only on: ESP32
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CONFIG_XTAL_FREQ_AUTO=y
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# ESP System Settings
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# Only on: ESP32, ESP32S3
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CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=n
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CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=n
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# Power Management
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CONFIG_PM_ENABLE=y
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# Memory protection
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# This is required to allow allocating IRAM
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CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=n
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# FreeRTOS
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CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=2
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CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
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CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP=n
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# UDP
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CONFIG_LWIP_PPP_SUPPORT=y
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CONFIG_LWIP_PPP_PAP_SUPPORT=y
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CONFIG_LWIP_PPP_CHAP_SUPPORT=y
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# SSL
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# Use 4kiB output buffer instead of default 16kiB
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CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y
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CONFIG_MBEDTLS_HAVE_TIME_DATE=y
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CONFIG_MBEDTLS_PLATFORM_TIME_ALT=y
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CONFIG_MBEDTLS_HAVE_TIME=y
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# Enable DTLS
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CONFIG_MBEDTLS_SSL_PROTO_DTLS=y
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# Disable ALPN support as it's not implemented in MicroPython
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CONFIG_MBEDTLS_SSL_ALPN=n
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# Disable slow or unused EC curves
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CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=n
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CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=n
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CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=n
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CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=n
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# Disable certificate bundle as it's not implemented in MicroPython
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CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=n
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CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=n
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# Enable PSK (pre-shared-key) cipher suites, used by tls.SSLContext PSK support.
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CONFIG_MBEDTLS_PSK_MODES=y
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CONFIG_MBEDTLS_KEY_EXCHANGE_PSK=y
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CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_PSK=y
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CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK=y
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CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_PSK=y
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# Allow mbedTLS to allocate from PSRAM or internal memory
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#
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# (The ESP-IDF default is internal-only, partly for physical security to prevent
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# possible information leakage from unencrypted PSRAM contents on the original
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# ESP32 - no PSRAM encryption on that chip. MicroPython doesn't support flash
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# encryption and is already storing the Python heap in PSRAM so this isn't a
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# significant factor in overall physical security.)
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CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC=y
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# ULP coprocessor support
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# Only on: ESP32, ESP32S2, ESP32S3
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CONFIG_ULP_COPROC_ENABLED=y
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CONFIG_ULP_COPROC_TYPE_FSM=y
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CONFIG_ULP_COPROC_RESERVE_MEM=2040
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# For cmake build
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CONFIG_ESPTOOLPY_FLASHSIZE_16MB=y
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CONFIG_PARTITION_TABLE_CUSTOM=y
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CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions-16MiBplus.csv"
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# To reduce IRAM usage
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CONFIG_ESP_WIFI_IRAM_OPT=n
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CONFIG_ESP_WIFI_EXTRA_IRAM_OPT=n
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CONFIG_ESP_WIFI_RX_IRAM_OPT=n
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CONFIG_ESP_WIFI_SLP_IRAM_OPT=n
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CONFIG_ESP_PHY_IRAM_OPT=n
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CONFIG_I2C_MASTER_ISR_HANDLER_IN_IRAM=n
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CONFIG_RMT_TX_ISR_HANDLER_IN_IRAM=n
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CONFIG_RMT_RX_ISR_HANDLER_IN_IRAM=n
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CONFIG_SPI_MASTER_ISR_IN_IRAM=n
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CONFIG_SPI_SLAVE_ISR_IN_IRAM=n
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CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=n
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CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=n
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# Legacy ADC Calibration Configuration
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# Only on: ESP32
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CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y
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CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y
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CONFIG_ADC_CAL_LUT_ENABLE=y
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# UART Configuration
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CONFIG_UART_ISR_IN_IRAM=y
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# IDF 5 deprecated
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CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN=y
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CONFIG_TOUCH_SUPPRESS_DEPRECATE_WARN=y
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CONFIG_ETH_USE_SPI_ETHERNET=y
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CONFIG_ETH_SPI_ETHERNET_W5500=y
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CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL=y
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CONFIG_ETH_SPI_ETHERNET_DM9051=y
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# Using newlib "nano" formatting saves size on SoCs where "nano" formatting
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# functions are in ROM. ESP32-C6 (and possibly other new chips) have "full"
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# newlib formatting in ROM instead and should override this, check
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# ESP_ROM_HAS_NEWLIB_NANO_FORMAT in ESP-IDF.
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CONFIG_NEWLIB_NANO_FORMAT=y
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# IRAM/DRAM split protection is a memory protection feature on some parts
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# that support SOC_CPU_IDRAM_SPLIT_USING_PMP, eg. C2, C5, C6, H2
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# Due to limitations in the PMP system this feature breaks native emitters
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# so is disabled by default.
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CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT=n
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# Further limit total sockets in TIME-WAIT when there are many short-lived
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# connections.
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CONFIG_LWIP_MAX_ACTIVE_TCP=12
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# Enable new I2C slave API, and disable conflict check.
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CONFIG_I2C_SKIP_LEGACY_CONFLICT_CHECK=y
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CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2=y

‎ports/esp32/machine_i2s.c‎

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@@ -49,6 +49,16 @@
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// The size of 240 bytes is an engineering optimum that balances transfer performance with an acceptable use of heap space
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#define SIZEOF_TRANSFORM_BUFFER_IN_BYTES (240)
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#ifndef SOC_I2S_NUM
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#if defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32S31)
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#define SOC_I2S_NUM 2
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#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32C6) || defined(CONFIG_IDF_TARGET_ESP32H2)
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#define SOC_I2S_NUM 1
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#else
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#define SOC_I2S_NUM 2
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#endif
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#endif
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typedef enum {
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I2S_TX_TRANSFER,
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I2S_RX_TRANSFER,
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typedef struct _machine_i2s_obj_t {
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mp_obj_base_t base;
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i2s_port_t i2s_id;
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int i2s_id;
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i2s_chan_handle_t i2s_chan_handle;
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mp_hal_pin_obj_t sck;
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mp_hal_pin_obj_t ws;
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};
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void machine_i2s_init0() {
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for (i2s_port_t p = 0; p < I2S_NUM_AUTO; p++) {
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for (int p = 0; p < SOC_I2S_NUM; p++) {
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MP_STATE_PORT(machine_i2s_obj)[p] = NULL;
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}
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}
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}
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static machine_i2s_obj_t *mp_machine_i2s_make_new_instance(mp_int_t i2s_id) {
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if (i2s_id < 0 || i2s_id >= I2S_NUM_AUTO) {
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if (i2s_id < 0 || i2s_id >= SOC_I2S_NUM) {
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mp_raise_ValueError(MP_ERROR_TEXT("invalid id"));
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}
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‎ports/esp32/mpconfigport.h‎

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#define MICROPY_PY_MACHINE_DAC (SOC_DAC_SUPPORTED)
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#endif
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#ifndef MICROPY_PY_MACHINE_I2S
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#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(6, 0, 0)
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#define MICROPY_PY_MACHINE_I2S (0)
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#else
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#define MICROPY_PY_MACHINE_I2S (SOC_I2S_SUPPORTED)
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#endif
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#endif
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#define MICROPY_PY_MACHINE_I2S_INCLUDEFILE "ports/esp32/machine_i2s.c"
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#define MICROPY_PY_MACHINE_I2S_FINALISER (1)
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#define MICROPY_PY_MACHINE_I2S_CONSTANT_RX (I2S_DIR_RX)

‎ports/esp32/partitions-16MiBplus.csv‎

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# This partition table is for devices with 4MiB or more of flash.
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# The first 2MiB is used for bootloader, nvs, phy_init and firmware.
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# The remaining flash is for the user filesystem(s).
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# Notes: the offset of the partition table itself is set in
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# $IDF_PATH/components/partition_table/Kconfig.projbuild.
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# Name, Type, SubType, Offset, Size, Flags
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nvs, data, nvs, 0x9000, 0x6000,
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phy_init, data, phy, 0xf000, 0x1000,
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factory, app, factory, 0x10000, 0x230000,

‎ports/esp32/partitions-4MiBplus.csv‎

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# Name, Type, SubType, Offset, Size, Flags
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nvs, data, nvs, 0x9000, 0x6000,
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phy_init, data, phy, 0xf000, 0x1000,
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factory, app, factory, 0x10000, 0x220000,
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factory, app, factory, 0x10000, 0x1F0000,

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