Pinned Loading

1. 5-stage-Pipelined-Harvard-Processor 5-stage-Pipelined-Harvard-Processor Public

   A pipelined, five-stage Harvard, RISC-ISA, Processor implemented in VHDL, supporting Branch Prediction, Interrupt Handling, Exception Handling, etc... An Assembler is implemented in C++

   VHDL

2. Analog-IC-Design Analog-IC-Design Public

   A sub-collection of my work related to Analog IC Design.

3. puf-fuzzy-extractor puf-fuzzy-extractor Public

   Hardware security implementation for extracting, characterizing, and stabilizing SRAM PUFs on Lattice iCE40 FPGAs. Features a Verilog-based entropy harvester and a Python-based Reed-Solomon Fuzzy E…

   Verilog

4. eecs316-digital-modulation eecs316-digital-modulation Public

   MATLAB Implementation of various digital modulation techniques

   MATLAB

5. OS-Scheduler OS-Scheduler Public

   A CPU Process Scheduler with Memory Management Unit

   C

6. aes-128 aes-128 Public

   modular AES-128 hardware accelerator implemented in Verilog for the Lattice iCE40 FPGA. The project includes synthesis and implementation using the OSS CAD Suite (Yosys + nextpnr), comprehensive C…

   Verilog