There's nothing I'd rather do than explore the mysteries of that interesting chip with fragmented documentation, but that will have to wait until Summer 2026
The reason being the lack of contiguous time that I freely dispose of as a human in modern-day society
In the meantime enjoy what little code I have for you, consult the General E24 core documentation, and submit issues or ideas for current or future projects
This project aims to document and shed light on parts of the BouffaloLab602
32-bit Wifi+BLE RV32IMFCX_Zifencei_Zicsr_Zaamo RISC-V SiFive E24 Core (No bitmanip extension)
single core microcontroller through practical examples written in Assembly language
This Repository was created out of frustration due to a general lack of good documentation
and practical bare-metal code examples for an otherwise amazing RISC-V embedded chip, as well as curiosity for the RISC-V ISA and assembly language
There's also other cool RISC-V microcontrollers, like the RP2350/4A/B (with bitmanip), or ESP32-C/H/P series chips
My goal is to improve documantation bit by byte by providing clean Assembly code,
through which the reader can get an understanding of how exactly they are supposed to interface
with internals and peripherals through MMIO without any confusing HALs or SDKs
I will try to incrementally grow this collection of small programs and maintain it with my best efforts
All example code is assembled tested on the PineCone EVB (I also have binaries available)
- PineCone schematics
- General E24 core documentation
- SiFive CLIC specifications
- CLIC/CLINT adress mapping
Directly controlling GPIO
MMIO mapping and hardware notes
- RISC-V Instruction Encoder/Decoder
- RISC-V ISA Manual
- Official ISA Specs by RISC-V International
Disassembly with Ghidra
- VSCodium code editor
- GCC (riscv64-linux-gnu-gcc & riscv64-linux-gnu-objcopy)
- Flasher utility: Blflash on Ubuntu, Blisp on Arch Linux
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